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  • Asia Communications and Photonics Conference (ACP) 2018
  • OSA Technical Digest (Optica Publishing Group, 2018),
  • paper Su3D.4

Real-time implementation of parallel digital timing recovery algorithm with reduced complexity

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Abstract

A real-time parallel all digital timing-recovery algorithm is implemented and investigated in a FPGA based 2.5Gbaud/s QPSK/16QAM system. Based on sharing numerically controlled oscillator, the complexity is reduced by at least 16% without performance degradation.

© 2018 The Author(s)

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