Expand this Topic clickable element to expand a topic
Skip to content
Optica Publishing Group

High Density Silicon Photonic Integrated Transceiver Chip with 1.2 Tbps Capacity

Not Accessible

Your library or personal account may give you access

Abstract

To achieve high capacity, high density, low power consumption and low-cost non-hermetic package, a silicon photonic transceiver chip with 42-channel I/O was demonstrated. With each I/O supports 28 Gbps rate, the transceiver chip reached 1.2 Tbps capacity.

© 2016 Optical Society of America

PDF Article
More Like This
2.56 Tbps (8 × 8 × 40 Gbps) Fully-Integrated Silicon Photonic Interconnection Circuit

Chong Zhang, Shangjian Zhang, Jon D. Peters, and John E. Bowers
JTh4C.4 CLEO: Applications and Technology (CLEO:A&T) 2016

Ultra-dense Silicon Photonics Coupling Solution for Optical Chip Scale Package Transceiver

Qing Zhao, Xiaolu Song, Zhen Dong, Lei Gao, Ruiqiang Ji, Yanbo Li, Ling Hao, Shengmeng Fu, and Li Zeng
AF4F.4 Asia Communications and Photonics Conference (ACP) 2016

3.2Tb/s Heterogeneous Photonic Integrated Circuit Chip in a Co-Packaged Optics Configuration

Damien Lambert, Jeff Rahn, Majid Sodagar, Murtaza Askari, Paveen Apiratikul, John Spann, Thang Pham, Yishen Huang, and Stephen Krasulick
W3D.2 Optical Fiber Communication Conference (OFC) 2023

Select as filters


Select Topics Cancel
© Copyright 2024 | Optica Publishing Group. All rights reserved, including rights for text and data mining and training of artificial technologies or similar technologies.