Abstract
We propose a bit pattern monitoring technique which effectively mitigates the random walk clock drift between data signal and sampling source in asynchronously undersampling systems. The method is verified by measurements of 40 Gb/s NRZ and 160 Gb/s RZ data signals. Quantitative analysis of the displayed timing jitter is performed.
© 2009 OSA, IEEE Photonics Society, SPIE, COS, CIC
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