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40 Gbit/s On-Off-Keyed System with 5.71 GHz Clock Recovery Circuit using Duty Cycle Division Multiplexing

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Abstract

We show the realization of 40 Gbit/s on-off-keyed system that can be recovered at 5.71 GHz clock using duty cycle division multiplexing technique with the receiver sensitivity of –22.1 dBm.

© 2009 OSA, IEEE Photonics Society, SPIE, COS, CIC

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